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A digital signal processor DSP is a specialized microprocessor or a SIP block , with its architecture optimized for the operational needs of digital signal processing. The goal of DSPs is usually to measure, filter or compress continuous real-world analog signals.
Most general-purpose microprocessors can also execute digital signal processing algorithms successfully, but dedicated DSPs usually have better power efficiency thus they are more suitable in portable devices such as mobile phones because of power consumption constraints. Digital signal processing algorithms typically require a large number of mathematical operations to be performed quickly and repeatedly on a series of data samples.
Signals perhaps from audio or video sensors are constantly converted from analog to digital, manipulated digitally, and then converted back to analog form. Many DSP applications have constraints on latency ; that is, for the system to work, the DSP operation must be completed within some fixed time, and deferred or batch processing is not viable.
Most general-purpose microprocessors and operating systems can execute DSP algorithms successfully, but are not suitable for use in portable devices such as mobile phones and PDAs because of power efficiency constraints.
The architecture of a digital signal processor is optimized specifically for digital signal processing. Most also support some of the features as an applications processor or microcontroller, since signal processing is rarely the only task of a system.
Some useful features for optimizing DSP algorithms are outlined below. By the standards of general-purpose processors, DSP instruction sets are often highly irregular; while traditional instruction sets are made up of more general instructions that allow them to perform a wider variety of operations, instruction sets optimized for digital signal processing contain instructions for common mathematical operations that occur frequently in DSP calculations. Both traditional and DSP-optimized instruction sets are able to compute any arbitrary operation but an operation that might require multiple ARM or x86 instructions to compute might require only one instruction in a DSP optimized instruction set.
One implication for software architecture is that hand-optimized assembly-code routines are commonly packaged into libraries for re-use, instead of relying on advanced compiler technologies to handle essential algorithms.
In engineering, hardware architecture refers to the identification of a system's physical components and their interrelationships. This description, often called a hardware design model, allows hardware designers to understand how their components fit into a system architecture and provides to software component designers important information needed for software development and integration.
Clear definition of a hardware architecture allows the various traditional engineering disciplines e. Hardware is also an expression used within the computer engineering industry to explicitly distinguish the electronic computer hardware from the software that runs on it. But hardware, within the automation and software engineering disciplines, need not simply be a computer of some sort.
A modern automobile runs vastly more software than the Apollo spacecraft. Also, modern aircraft cannot function without running tens of millions of computer instructions embedded and distributed throughout the aircraft and resident in both standard computer hardware and in specialized hardware components such as IC wired logic gates, analog and hybrid devices, and other digital components.
The need to effectively model how separate physical components combine to form complex systems is important over a wide range of applications, including computers, personal digital assistants PDAs , cell phones, surgical instrumentation, satellites, and submarines. DSPs are usually optimized for streaming data and use special memory architectures that are able to fetch multiple data or instructions at the same time, such as the Harvard architecture or Modified von Neumann architecture , which use separate program and data memories sometimes even concurrent access on multiple data buses.
DSPs can sometimes rely on supporting code to know about cache hierarchies and the associated delays. This is a tradeoff that allows for better performance [ clarification needed ]. In addition, extensive use of DMA is employed. DSPs frequently use multi-tasking operating systems, but have no support for virtual memory or memory protection. Operating systems that use virtual memory require more time for context switching among processes , which increases latency.
Prior to the advent of stand-alone DSP chips discussed below, most DSP applications were implemented using bit-slice processors. The AMD bit-slice chip with its family of components was a very popular choice. There were reference designs from AMD, but very often the specifics of a particular design were application specific. These bit slice architectures would sometimes include a peripheral multiplier chip. It also set other milestones, being the first chip to use Linear predictive coding to perform speech synthesis.
In , Intel released the as an "analog signal processor". In , AMI released the S It was designed as a microprocessor peripheral, and it had to be initialized by the host. The S was likewise not successful in the market. Both processors were inspired by the research in PSTN telecommunications. The Altamira DX-1 was another early DSP, utilizing quad integer pipelines with delayed branches and branch prediction.
It was based on the Harvard architecture, and so had separate instruction and data memory. It already had a special instruction set, with instructions like load-and-accumulate or multiply-and-accumulate. TI is now the market leader in general-purpose DSPs. About five years later, the second generation of DSPs began to spread. They had 3 memories for storing two operands simultaneously and included hardware to accelerate tight loops ; they also had an addressing unit capable of loop-addressing.
The main improvement in the third generation was the appearance of application-specific units and instructions in the data path, or sometimes as coprocessors. These units allowed direct hardware acceleration of very specific but complex mathematical problems, like the Fourier-transform or matrix operations.
Some chips, like the Motorola MC, even included more than one processor core to work in parallel. Modern signal processors yield greater performance; this is due in part to both technological and architectural advancements like lower design rules, fast-access two-level cache, E DMA circuitry and a wider bus system.
TMSC chips each have three such DSPs, and the newest generation C chips support floating point as well as fixed point processing. The processors have a multi-threaded architecture that allows up to 8 real-time threads per core, meaning that a 4 core device would support up to 32 real time threads. The devices are easily programmable in C and aim at bridging the gap between conventional micro-controllers and FPGAs. The Blackfin family of embedded digital signal processors combine the features of a DSP with those of a general use processor.
The TriMedia media processors support both fixed-point arithmetic as well as floating-point arithmetic , and have specific instructions to deal with complex filters and entropy coding. Introduced in  , the dsPIC is designed for applications needing a true DSP as well as a true microcontroller , such as motor control and in power supplies. Most DSPs use fixed-point arithmetic, because in real world signal processing the additional range provided by floating point is not needed, and there is a large speed benefit and cost benefit due to reduced hardware complexity.
Floating point DSPs may be invaluable in applications where a wide dynamic range is required. Product developers might also use floating point DSPs to reduce the cost and complexity of software development in exchange for more expensive hardware, since it is generally easier to implement algorithms in floating point.
From Wikipedia, the free encyclopedia. Process Control and Optimization. Instruction pipelining Bubble Operand forwarding Out-of-order execution Register renaming Speculative execution Branch predictor Memory dependence prediction Hazards. Single-core processor Multi-core processor Manycore processor. History of general-purpose CPUs. Retrieved from " https: Digital signal processing Digital signal processors Integrated circuits Coprocessors.